A variety of methods for generating cyclic redundancy check (CRC) codes are proposed in the prior art. For example, there is proposed a CRC code calculation method in which the calculation of a CRC on parallel input data is performed by re-expanding the parallel input data and by performing the sub-operations of divisions using the technique of pipeline processing. This method is intended to speed up the calculation process by preventing the number of circuit stages in an exclusive-OR circuit network from increasing in connection with the parallel expansion.
In the above method, data input from an input terminal is expanded by an expansion circuit into two parts on a word-by-word basis, and the CRC code for the input data is calculated using two first sub-operation circuits and one second sub-operation circuit. When generating the CRC code, the CRC code is appended to the final data word by a selector circuit, and the data and the CRC code are output from an even-numbered word output terminal and an odd-numbered word output terminal. When checking the CRC code, the data is checked by a check circuit for data errors after all the data has been input and, if any error is detected, the check circuit outputs a “high” signal at its output terminal.
There is also proposed a CRC code generating method that generates a CRC code using minimum information by constructing a logic circuit based on a given number of precalculated CRC codes but without using a division circuit or a ROM. The method includes the step of precalculating a number, n, of partial CRC codes corresponding to the respective bits of an n-bit operation bit sequence and the step of obtaining a CRC code for the entire n-bit operation bit sequence by using the values of the partial CRC codes, based on the effective value of each bit in the n-bit operation bit sequence. In the step of obtaining the CRC code, the CRC code for the entire n-bit operation bit sequence is obtained by decoding the effective value of each bit of the n-bit operation bit sequence into a partial CRC code by taking an exclusive-OR sum.
There is also proposed an error-detecting code generating circuit that can perform processing by using the number of parallel processes that exceeds the degree of the generating polynomial. In this method, a data sequence is divided into n sub-data sequences, 1, 2, . . . , n, the respective sub-data sequences are processed independently of each other, and after data processing of all the sub-data sequences is completed, the exclusive-OR of the processing results are calculated. In each process, an operation that matches the number, n, of divisions is performed on the sub-data sequence preceding the last data of the input sub-data sequence, and an operation that matches the sub-data sequence, 1, 2, . . . , n, is performed on the last data that is input to each processing means.
Related art is disclosed in Japanese Laid-open Patent Publications No. 8-330976, No. 8-149017 and No. 9-64754.